JPH0432774Y2 - - Google Patents
Info
- Publication number
- JPH0432774Y2 JPH0432774Y2 JP1984072215U JP7221584U JPH0432774Y2 JP H0432774 Y2 JPH0432774 Y2 JP H0432774Y2 JP 1984072215 U JP1984072215 U JP 1984072215U JP 7221584 U JP7221584 U JP 7221584U JP H0432774 Y2 JPH0432774 Y2 JP H0432774Y2
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- wire
- bonding part
- unit light
- emitting diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 238000003780 insertion Methods 0.000 description 10
- 230000037431 insertion Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002730 additional effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984072215U JPS60183460U (ja) | 1984-05-16 | 1984-05-16 | 単位発光ダイオ−ドの集合体 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984072215U JPS60183460U (ja) | 1984-05-16 | 1984-05-16 | 単位発光ダイオ−ドの集合体 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60183460U JPS60183460U (ja) | 1985-12-05 |
| JPH0432774Y2 true JPH0432774Y2 (en]) | 1992-08-06 |
Family
ID=30610421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984072215U Granted JPS60183460U (ja) | 1984-05-16 | 1984-05-16 | 単位発光ダイオ−ドの集合体 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60183460U (en]) |
-
1984
- 1984-05-16 JP JP1984072215U patent/JPS60183460U/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60183460U (ja) | 1985-12-05 |
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